1. Field of the Invention
The present invention relates to semiconductor design and manufacturing. More specifically, the present invention relates to a method and an apparatus for facilitating variation-aware parasitic extraction.
2. Related Art
Process variation related yield loss is becoming dominant in nanometer technologies. Higher circuit speeds and increasing relative variations in the design parameters have created a strong need for variation-aware tools, such as, variation aware static timing analysis (VA-STA). Further, simulation-based analysis of integrated circuits is typically performed using spice models for devices and interconnect models for wires. Both of these models must become variation aware for VA-STA to be practical.
Full-chip parasitic extraction usually employs a template matching approach which involves generating capacitance tables using a set of capacitance models which are associated with frequently encountered interconnect templates. Unfortunately, generating capacitance tables typically requires vast amounts of computation because of at least two reasons. First, a large number of interconnect templates are required to adequately cover the geometries that are usually encountered in an integrated circuit. Second, determining the parasitic capacitance for each interconnect template involves generating and solving large sets of simultaneous linear equations. Specifically, a numerical discretization technique such as BEM (Boundary Element Method), FDM (Finite Difference Method), FEM (Finite Element Method), can be used for generating these sets of simultaneous linear equations. The numerical discretization technique generates simultaneous linear equations by discretizing the Laplacian of the partial differential equations that describe the capacitance for an interconnect template. The simultaneous linear equations can then be solved using a linear equation solver.
Note that determining the capacitance of a single interconnect template can involve solving a system of linear equations that contains thousands of variables. Further, capacitance tables usually contain hundreds of thousands of interconnect templates to adequately cover all the interconnect configurations. Consequently, generating capacitance tables usually requires solving hundreds of millions of systems of linear equations. This can be an enormously time consuming process even for today's high performance computers. Furthermore, advances in process technologies are expected to result in more complex geometries, larger number of metal layers, and more stringent accuracy requirements. All of these developments will further increase the computational demands.
A single set of capacitance tables may be sufficient if the process parameters are deterministic, i.e., the parameters do not have any variation. Unfortunately, process parameters often vary from their nominal values due to random variations in the manufacturing processes. Prior art capacitance extraction techniques can be used to model parameter variation by generating capacitance tables for a large number of process corners. It is evident that such approaches will require an almost infeasible amount of computation. Hence, for all practical purposes, generating capacitance tables for a sufficiently large number of process corners is computationally infeasible.
To overcome the computational burden, some prior art techniques sacrifice accuracy. For example, in a process corner based approach, perfectly correlated extreme variations can be used for all metal and dielectric layers. Unfortunately, the perfect correlation assumption is unrealistic because these process steps occur at different times in the fabrication flow, and hence are independent of one another. Further, there is no guarantee that the combinations of extreme parameter variations cover the actual best-case or worst-case scenarios in terms of timing delay or crosstalk analysis.
Hence, what is needed is a method and an apparatus for facilitating variation-aware parasitic extraction.